1. Field of the Invention
The present invention relates generally to technology for programming memory devices.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Typical EEPROMs and flash memories utilize a memory cell with a floating gate that is provided above and insulated from a channel region in a semiconductor substrate. The channel region is positioned in a p-well between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the memory cell is controlled by the amount of charge that is retained on the floating gate. That is, the level of charge on the floating gate determines the minimum amount of voltage that must be applied to the control gate before the memory cell is turned on to permit conduction between its source and drain.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states. A multi-bit or multi-state flash memory cell is implemented by identifying multiple, distinct threshold voltage ranges within a device. Each distinct threshold voltage range corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. For example, U.S. Pat. No. 6,222,762 and U.S. patent application Ser. No. 10/461,244, “Tracking Cells For A Memory System,” filed on Jun. 13, 2003, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells. To achieve proper data storage for a multi-state cell, the multiple ranges of threshold voltage levels of the multi-state memory cell should be separated from each other by sufficient margin so that the level of the memory cell can be programmed or erased in an unambiguous manner.
When programming an EEPROM or flash memory device, a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised.
Typically, the program voltage Vpgm applied to the control gate is applied as a series of pulses, as depicted in FIG. 1. The magnitude of the pulses is increased with each successive pulse by a predetermined step size (e.g. 0.2 v). In the periods between the pulses, verify operations are carried out. That is, the programming level of each cell of a group of cells being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than a verify level to which it is being programmed. One means of verifying the programming is to test conduction at a specific compare point. The cells that are verified to be sufficiently programmed are locked out, for example, by raising the bit line voltage from 0 to Vdd to stop the programming process for those cells. For example, FIG. 2 depicts graphs of threshold voltage (Vth) versus time and bit line voltage (Vbl) versus time. While the memory cell is receiving the program voltage Vpgm of FIG. 1, the threshold voltage of the memory cell increases. When the threshold voltage of the memory cell reaches the verify level (e.g. Vver1), then the bit line voltage is raised to Vinhibit (e.g. Vdd). The above described techniques, and others described herein, can be used in combination with various self boosting techniques, for example, as described in U.S. patent application Ser. No. 10/379,608, titled “Self Boosting Technique,” filed on Mar. 5, 2003, incorporated herein by reference in its entirety. Additionally, an efficient verify technique can be used, such as described in U.S. patent application Ser. No. 10/314,055, “Smart Verify for Multi-State Memories,” filed Dec. 5, 2002, incorporated herein by reference in its entirety.
When programming as depicted in FIG. 2, there is a tradeoff between speed of programming and precision of programming. The precision of programming is related to the distribution of threshold voltages of the programmed memory cells subsequent to the programming process. The tighter the threshold voltage distribution, the easier it is to unambiguously read the memory cells. The need for tight threshold voltage distributions is even more important with multi-state memory cells because the read process needs to unambiguously distinguish between the different threshold voltage distributions. To obtain a tight threshold voltage distribution, a smaller step size is used for the program voltage Vpgm. However, using a smaller step size slows down the programming process.
An improvement to the traditional programming process is depicted in FIG. 3. The process of FIG. 3 applies the program voltage signal Vpgm of FIG. 1 to the control gates of the memory cells to be programmed. Between the program pulses, verify operations are performed. If the threshold voltage of the memory cell being programmed is less than Vver2, the programming continues for that cell with the bit line voltage remaining low (e.g. 0 volts). If the threshold voltage of the memory cell being programmed is higher than Vver2 and lower than Vver1, then an intermediate bit line voltage (e.g. 1 volt) is applied. As a result of the intermediate bit line voltage, the channel voltage will increase (e.g. 1 volt) and the programming of that memory cell will be slowed down because the shift in threshold voltage due to each program pulse will be reduced. The bit line will remain at the intermediate bit line voltage for a number of pulses until the threshold voltage of the memory cell reaches the final target, Vver1. When the memory cell's threshold voltage reaches Vver1, the bit line will be raised to inhibit further programming (e.g. by raising the bit line voltage to Vinhibit (e.g. Vdd)).
Using the approach of FIG. 3 results in the programmed threshold voltage distribution being narrower than the process of FIG. 2 because the shift per pulse of the threshold voltage is reduced once the threshold voltage is close to the target value (e.g. when the threshold voltage is above Vvere2 and below Vver1). However, the speed of the programming process of FIG. 3 could be improved because multiple additional pulses (e.g. typically, 2 to 3 pulses) may be needed to finish the programming process since the intermediate bit line bias slows down the programming of the memory cells.
Another issue with prior memory systems relates to power. Many previous systems use a Vdd of 3 volts. It is advantageous to use a lower Vdd because a lower Vdd allows the memory system to use less power. If the memory system uses less power, the host device (e.g. digital camera) will have a longer battery life. If Vdd is reduced (e.g. to 1.8 volts), the memory cells may not be able to use an intermediate bit line voltage of 1 volt. For example, in a NAND chain with a select gate transistor (see discussion below), if the lower Vdd (e.g. 1.8 volts) is applied to the gate of the select gate transistor to turn on the select gate transistor, then the 1V bit line voltage may not be fully transferred to the source side of the select transistor. The voltage that can be transferred to the source side depends on the threshold voltage of the select gate transistor. If for example, the select gate has a threshold voltage of 1.2V, then the voltage at the source side of the select gate will only reach a value of 0.6V-1.8V (gate voltage)−1.2V (threshold voltage). It is possible to transfer 1V to the source side by lowering the threshold voltage of the select gate transistor; however, then the leakage of that transistor will increase in the case when the select gate is turned off (0V at the select gate). Another solution would be to increase the gate voltage of the select gate to for example 2.4V, however, in that case, during programming, leakage from the channel region towards the bit line may occur during a so called self-boosting operation when 1.8V is applied to the bit line and the channel area under the selected NAND string is boosted to a high voltage.